1. Technical Field
The present invention generally relates to logic changes in integrated circuit design, and more specifically to maintaining proper timing closure when such changes are made.
2. Description of Related Art
Timing closure of logic designs becomes more challenging as circuit elements decrease in size and increase in speed. When logic changes are made (e.g., an element is added) in an engineering change order (ECO), extra or spare cells, already existing in the design, are typically used. Extra or spare cells are defined as any logic element intentionally placed by the designer for the use of future ECOs or cells freed up for use after a previous ECO logic change.
In many cases, the extra logic that is intentionally placed by the designer in previous revisions of silicon (e.g., during full layer spins) is not in an ideal location with respect to timing closure. Spare elements are therefore more cheaply connected to the desired logic path by creating interconnects between them, which can be done in a metal-only spin—a cheaper process than a full layer spin. Typically, existing extra logic cells or elements are placed in any spare area of the silicon, which may be distant from the desired location for the added element. The timing delay introduced by routing to the extra cell logic element is detrimental and can cause timing closure failure.
There are often other logic paths nearby the preferred location for the new element. Often, these nearby logic paths have enough leeway in their timing closure to endure added delay while still maintaining timing closure. However, this timing leeway of nearby logic paths is not currently taken advantage of when implementing ECOs.
Hence, there is a need in the art for a system and method of achieving timing closure for logic changes that avoids these problems.